Testable And Reliable Systems Laboratory


Lab Name and Affiliation

Testable And Reliable Systems Laboratory

National Sun Yat-sen University College of Engineering Department of Electrical Engineering

Lab Director (or Principal Investigator)

Tong-Yu Hsieh
Tong-Yu Hsieh was born in Kaohsiung, Taiwan, in 1982. He received the B.S. and Ph.D. degree in electrical engineering from National Cheng Kung University in 2004 and 2009, respectively. He was also a visiting scholar in department of electrical engineering of University of Southern California, Los Angeles, USA during 2008-2009. In 2011 he joined the Department of Electrical Engineering, National Sun Yat-Sen University, Taiwan, and is currently an assistant professor. His recent research interests include VLSI design and testing, reliability and yield improvement and computer-aided design. He has been a member of IEEE Circuits and Systems Society since 2005.

Lab Introduction

Testable And Reliable Systems Lab. (TARSys Lab.) was found in 2011, which targets enhancing testability and reliability of SOC systems. Currently we are focusing on multimedia processing circuits and processor designs based on error-tolerance and performance-degradation-tolerance. Error-tolerance and performance -degradation-tolerance are novel notions that can improve yield of VLSI circuits by identifying defective yet acceptable chips.

Different from defect-tolerance and fault-tolerance that ensure that no error would appear at outputs of a circuit, error-tolerance can allow the appearance of minor errors at circuit outputs by exploiting the fact that human beings are insensitive to such errors. This notion is applicable to circuits related to the human sensory system (e.g., visual system, auditory system, etc.), such as multimedia signal processing circuits.

The focus of performance-degradation-tolerance is on the particular performance degrading faults (pdef) that only induce some performance degradation of a system without resulting in any errors for the computational results. The basic idea is that as long as the defective chips that contain only pdef can provide acceptable performance for some applications, they may still be marketable. It has been shown that this notion is applicable to many components in a high-performance processor design that are dedicated for enhancing the system performance, such as branch predictors.

Lab members include 2 Ph.D. students and 7 master students. Up to now, 3 masters graduated from our lab.

Lab Contact E-mail