Communications and Signal Processing IC Design (CaSIC) Lab


Lab Name and Affiliation

Communications and Signal Processing IC Design (CaSIC) Lab

National Chiao Tung University, Hsinchu, Taiwan

Lab Director (or Principal Investigator)

Shang-Ho (Lawrence) Tsai received the Ph.D. degree in Electrical Engineering from the University of Southern California, USA, in Aug. 2005. From June 1999 to July 2002, he was with the Silicon Integrated Systems Corp. (SiS), where he participated the VLSI design for DMT-ADSL systems. From Sep. 2005 to Jan. 2007, he was with the MediaTek Inc. and participated the VLSI design for MIMO-OFDM systems. Since Feb. 2007, he joined the Department of Electrical and Control Engineering at the National Chiao Tung University (now department of Electrical Engineering) where he is now an associate professor.

His research interests include signal processing for communications, statistical signal processing, and signal processing for VLSI designs.

He was awarded a government scholarship for overseas study from the Ministry of Education, Taiwan, from Aug. 2002 to Aug. 2005. Currently he is a visiting fellow in Department of Electrical Engineering at Princeton University.

Lab Introduction

Communications and Signal Processing IC Design (CaSIC) Lab is devoted to the theoretical study and architecture design for communications and signal processing systems. Our current research activities include: signal processing for communications, MIMO techniques, multicarrier/OFDM/DMT systems and signal processing for VLSI. Our goals are to create feasible algorithm and Silicon IPs for current and future standards in industry as well as theoretical contributions for academia.

Lab Contact E-mail